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M16C/64C Group
SCL clock
Figure 23.26 SCL Clock
23.3.3.6
SDA Output Control
When transmitting byte data, the SDAi pin outputs transmit data for the first to eighth bits, and it is
released to receive an acknowledgment for the ninth bit.
2
In I
C mode, set 9-bit data to the UiTB register. In 9-bit data, set the transmit data to bits b7 to b0 and
set b8 to 1. By setting the UFORM bit in the UiC0 register to 1 (MSB first) and 9-bit data to the UiTB
register, transmit data is output from the SDAi pin in the following order: b7, b6, b5, b4, b3, b2, b1, b0
and b8. As b8 is 1, the SDAi pin becomes high-impedance at the ninth bit and an acknowledgment can
be received.
Figure 23.27 UiTB Register Setting (SDA Output)
SCL
(Transmitter) SDA
Figure 23.28 Byte Data Transmission
Set bits DL2 to DL0 in the UiSMR3 register to add no delays or a delay of one to eight UiBRG count
source clock cycles to SDAi output.
Setting the SDHI bit in the UiSMR2 register to 1 (SDA output disabled) forcibly places the SDAi pin in a
high-impedance state. Do not write to the SDHI bit at the rising edge of the UARTi transmit/receive
clock as the ABT bit in the UiRB register may inadvertently become 1 (detected).
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
To be compatible with SCL low hold from another device, the
high time count starts after high is determined.
1 / (2f
(theoretical value))
SCL
t
t
LOW
F
UARTi Transmit Buffer Register (UiTB)
b15
1
b7
UiTB register ← 01XXh
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
1 / (2f
(theoretical value))
SCL
Noise filter width + 1 to 1.5 cycles
(high determined delay)
t
t
R
HIGH
b8
b7
1
Transmit data
Set to 1 to release the SDAi pin
2
3
4
5
b6
b5
b4
b3
Transmit data
b0
6
7
8
9
b2
b1
b0
b8
Release (Hi-Z)
Page 500 of 807
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