Uarti Special Mode Register (Uismr) (I = 0 To 2, 5 To 7) - Renesas M16C/64C User Manual

M16C/64C Group

23.2.12 UARTi Special Mode Register (UiSMR) (i = 0 to 2, 5 to 7)

UARTi Special Mode Register (i = 0 to 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1
0
BBS (Bus busy flag) (b2)
The BBS bit is set to 0 by a program. (It remains unchanged even if 1 is written.)
ABSCS (Bus collision detect sampling clock select bit) (b4)
When the ABSCS bit is 1, the combinations of UARTi and timer Aj are as follows:
UART0, UART6: Underflow signal of timer A3
UART1, UART7: Underflow signal of timer A4
UART2, UART5: Underflow signal of timer A0
SSS (Transmit start condition select bit) (b6)
When a transmission starts, the SSS bit becomes 0 (not synchronized to RXDi).
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Symbol
b0
U0SMR, U1SMR, U2SMR
U5SMR, U6SMR, U7SMR
Bit Symbol Bit Name
2
IICM I C mode select bit
Arbitration lost detect flag
ABC
control bit
BBS Bus busy flag
—
Reserved bit
(b3)
Bus collision detect sampling
ABSCS
clock select bit
Auto clear function select bit
ACSE
of transmit enable bit
Transmit start condition
SSS
select bit
—
No register bit. If necessary, set to 0. The read value is undefined.
(b7)
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Address
0247h, 0257h, 0267h
0287h, 0297h, 02A7h
Function
2
0 : Other than I C mode
2
1 : I C mode
0 : Update every bit
1 : Update every byte
0 : Stop-condition detected
1 : Start-condition detected (busy)
Set to 0
0 : Rising edge of transmit/receive clock
1 : Underflow signal of timer Aj
0 : No auto clear function
1 : Auto clear at bus collision
0 : Not synchronized to RXDi
1 : Synchronized to RXDi
Reset Value
X000 0000b
X000 0000b
RW
RW
RW
RW
RW
RW
RW
RW
—
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