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M16C/64C Group
22.3
Operations
22.3.1
Common Operations in Multiple Modes
22.3.1.1
Count Source
The clock source and divisor of the count source can be selected by bits CSRC1 to CSRC0 and bits
CDIV1 to CDIV0 in the PMCiCON3 register (see Figure 22.3 "Remote Control Signal Receiver Block
Diagram (3/3) (PMCi Count Source)").
When using fC, set the PM25 bit in the PM2 register to 1 (peripheral clock fC provided). Refer to
8. "Clock Generator" for details of fC.
When using timer B1 or B2 underflow, one cycle of the count source consists of one timer B1 or B2
underflow cycle. Use timer B1 or B2 in timer mode. Refer to 18. "Timer B" for details.
To use the same count source in PMC0 and PMC1, set bits CSRC1 to CSRC0 in the PMC0CON3
register to 00b (same count source as PMC1), and bits CDIV1 to CDIV0 in the PMC0CON3 register
to 00b (no division).
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
22. Remote Control Signal Receiver
Page 425 of 807
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