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M16C/64C Group
Table 23.6 lists Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transmit/Receive Clock
Output Pin Function Not Selected). Table 23.7 lists P6_4 Pin Functions in Clock Synchronous Serial I/O
Mode.
Note that for a period from when UARTi operating mode is selected to when transmission starts, the
TXDi pin outputs a high-level signal. (If N-channel open drain output is selected, this pin is high-
impedance.)
Table 23.6
Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transmit/Receive Clock
Output Pin Function Not Selected)
Pin Name
I/O
TXDi
Output
Input
RXDi
Input
Output
CLKi
Input
Input
CTSi / RTSi
Output
I/O
i = 0 to 2, 5 to 7
Table 23.7
P6_4 Pin Functions in Clock Synchronous Serial I/O Mode
Pin Function
P6_4
CTS1
RTS1
CTS0
(1)
CLKS1
- indicates either 0 or 1
Notes:
In addition to these settings, set the CRD bit in the U0C0 register to 0 ( CTS0 / RTS0 enabled)
1.
and the CRS bit in the U0C0 register to 1 ( RTS0 selected).
2.
When the CLKMD1 bit is 1 and the CLKMD0 bit is 0, the following logic levels are output:
•
High if the CLKPOL bit in the U1C0 register is 0
•
Low if the CLKPOL bit in the U1C0 register is 1
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Function
Serial data output
Serial data input
Input port
Transmit/receive
clock output
Transmit/receive
clock input
CTS input
RTS output
I/O port
U1C0 register
CRD
CRS
1
-
0
0
0
1
0
0
-
-
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Method of Selection
(Outputs dummy data only when receiving)
Set the port direction bit sharing pin to 0.
Set the port direction bit sharing pin to 0. (can be used as
an input port only when transmitting)
The CKDIR bit in the UiMR register = 0
The CKDIR bit in the UiMR register = 1
Set the port direction bit sharing pin to 0.
The CRD bit in the UiC0 register = 0
The CRS bit in the UiC0 register = 0
Set the port direction bit sharing pin to 0.
The CRD bit in the UiC0 register = 0
The CRS bit in the UiC0 register = 1
The CRD bit in the UiC0 register = 1
Bit Set Value
UCON register
RCSP
CLKMD1
0
0
0
0
0
0
1
0
(2)
-
1
PD6 register
CLKMD0
PD6_4
-
Input: 0, Output: 1
-
0
-
-
-
0
1
-
Page 472 of 807
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