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M16C/64C Group
26.3.5
Reception
26.3.5.1
Start Bit Detection
The detect timing of the start bit and data bit is selected by setting the CRRNG bit in the CEC2
register. Select the start bit acceptable range by setting the CSTRRNG bit in the CECC2 register.
Figure 26.5 shows Start Bit Acceptable Range.
When the start bit within the acceptable range is detected, the CRSTFLG bit in the CECFLG register
becomes 1 (start bit detected).
When the CRRNG bit is set to 0,
When the CRRNG bit is set to 1,
CEC input
Figure 26.5
Start Bit Acceptable Range
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
When the CSTRRNG bit is 0: ±200 µs
When the CSTRRNG bit is 1: ±300 µs
0 ms
CRRNG, CSTRRNG: Bits in the CECC2 register
26. Consumer Electronics Control (CEC) Function
Acceptable range
Acceptable range
±200 µs
±300 µs
3.7 ms
4.5 ms
Only a falling edge is detected
Both edges are detected
Page 600 of 807
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