Renesas M16C/64C User Manual page 351

M16C/64C Group
Event Counter Mode
Timer Bi Mode Register (i = 0 to 5)
b7 b6 b5 b4 b3 b2 b1
0
MR1 and MR0 (Count polarity select bit) (b3-b2)
These bits are enabled when the TCK1 bit is 0 (input from TBiIN pin). When the TCK1 bit is 1 (timer Bj),
these bits can be set to 0 or 1.
TCK1 (Event clock select bit) (b7)
When the TCK1 bit is 1, an event occurs when an interrupt request of timer Bj (j = i - 1; however, j = 2 if
i = 0, j = 5 if i = 3) is generated. An event occurs while an interrupt is disabled because an interrupt
request signal is generated regardless of the I flag, IPL, or interrupt control registers
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Symbol
b0
TB0MR to TB2MR
1
TB3MR to TB5MR
Bit Symbol Bit Name
TMOD0
Operation mode select bit
TMOD1
MR0
Count polarity select bit
MR1
—
No register bit. If necessary, set to 0. The read value is undefined.
(b4)
Write 0 in event counter mode.
MR3
The read value is undefined in event counter mode
Disabled in event counter mode.
TCK0
Set 0 or 1.
TCK1 Event clock select bit
Address
033Bh to 033Dh
031Bh to 031Dh
Function
b1 b0
0 1 : Event counter mode
b3 b2
0 0 : Counts falling edges of an external
signal
0 1 : Counts rising edges of an external signal
1 0 : Counts falling and rising edges of an
external signal
1 1 : Do not set
0 : Input from TBiIN pin
1 : Timer Bj
(j = i - 1; however, j = 2 if i = 0, j = 5 if i = 3)
18. Timer B
Reset Value
00XX 0000b
00XX 0000b
RW
RW
RW
RW
RW
—
RO
RW
RW
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