Table of Contents
Advertisement
M16C/64C Group
7.4.4.2
Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
Table 7.8 lists Procedure for Setting Voltage Monitor 2 Interrupt/Reset Related Bits.
Table 7.8
Procedure for Setting Voltage Monitor 2 Interrupt/Reset Related Bits
Step
Voltage monitor 2
interrupt
1
Set the VW12E bit in the VWCE register to 1 (voltage monitors 1 and 2 enabled).
2
Set the VC27 bit in the VCR2 register to 1 (voltage detector 2 enabled).
3
Wait for td(E-A).
Set bits VW2F0 to VW2F1 in the VW2C
4
register to select the digital filter sampling
clock.
Set the VW2C1 bit in the VW2C register to 0
(2)
5
(digital filter enabled).
Set the VW2C6 bit in
the VW2C register to 0
(2)
6
(voltage monitor 2
interrupt).
7
Set the VW2C2 bit in the VW2C register to 0 (Vdet2 passage not detected).
Set the CM14 bit in the CM1 register to 0 (125
8
kHz on-chip oscillator on)
9
Wait for digital filter sampling clock x 3 cycles. - (no wait time)
10
Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled).
Notes:
1.
Set the VW2C7 bit to 1 (when VCC1 reaches Vdet2 or below) for the voltage monitor 2 reset.
2.
When the VW2C0 bit is 0, steps 4, 5, and 6 can be executed simultaneously (with one instruction).
3.
If the above settings are performed while the voltage monitor 2 interrupt/reset is disabled (VW2C0
bit in the VW2C register is 0, VC27 bit in the VCR2 register is 0), and VCC1 < Vdet2 (or VCC1 >
Vdet2) is detected before enabling the voltage monitor 2 interrupt/reset (step 10), an interrupt is
not generated. When VCC1 < Vdet2 (or VCC1 > Vdet2) is detected while executing steps 8 to 10,
the VW2C2 bit becomes 1.
When using this result detected between steps 8 and 10, read the VW2C2 bit after step 10. If the
bit is 1, execute the process to be performed after detecting the VCC1 < Vdet2 (or VCC1 > Vdet2).
When ignoring the result detected between steps 8 and 10, set the VW2C2 bit to 0 after step 10.
When using voltage monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1
bit in the VW2C register to 1 (digital filter disabled).
When voltage monitor 2 reset is generated, the LVD2R bit in the RSTFR register is automatically
becomes 1 (voltage monitor 2 reset detected). Refer to 6.4.6 "Voltage Monitor 2 Reset" for status
after reset.
Figure 7.8 shows Voltage Monitor 2 Interrupt/Reset Operation Example.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
When Using the Digital Filter
Voltage monitor 2
Set the VW2C6 bit in
the VW2C register to 1
(voltage monitor 2
reset).
When Not Using the Digital Filter
Voltage monitor 2
reset
interrupt
Set the VW2C7 bit in the VW2C register to
select the timing of the interrupt and reset
request.
Set the VW2C1 bit in the VW2C register to 1
(digital filter disabled).
Set the VW2C6 bit in
the VW2C register to 0
(voltage monitor 2
interrupt).
-
7. Voltage Detector
Voltage monitor 2
(1)
Set the VW2C6 bit in
the VW2C register to 1
(voltage monitor 2
reset).
reset
Page 80 of 807
Advertisement
Table of Contents
