Operations; A/D Conversion Cycle - Renesas M16C/64C User Manual

M16C/64C Group
27.3

Operations

27.3.1

A/D Conversion Cycle

A/D conversion cycle is based on fAD and φ AD. Divide fAD so φ AD conforms the standard frequency.
Figure 27.2 shows fAD and φ AD.
Set the PCKSTP1A bit in the PCLKSTP1 register to 0 (f1 provide enabled) when using f1 as the clock
source of fAD.
f1
CKS0: Bit in the ADCON0 register
CKS1: Bit in the ADCON1 register
CKS2: Bit in the ADCON2 register
fAD and φ AD
Figure 27.2
Figure 27.3 shows A/D Conversion Timing.
Start
processing
Start
processing
Processing
1 to 2
cycle
fAD
The above figure applies under the following conditions:
One-shot mode
φAD = fAD
Figure 27.3 A/D Conversion Timing
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
CKS2
0
fAD
1/3
fAD
1
Open-circuit
First bit conversion time
detection
Open-circuit
detection Sampling time
charge time
2 φAD 15 φAD
40 φAD
42 φAD
Select A/D conversion speed
1
0
1/2 1/2
CKS0
Second
Third bit
bit
Compare Compare Compare
time time time
25 φAD
27. A/D Converter
CKS1
1
φAD
0
End
Tenth bit
processing
Compare
End
time processing
2 to 3
fAD
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