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M16C/64C Group
25.3.7
Detecting Start/Stop Conditions
Figure 25.13 shows Start Condition Detection, Figure 25.14 shows Stop Condition Detection, and Table
25.14 lists Conditions to Detect Start/Stop Condition.
A start/stop condition can be detected only when the start/stop condition detect parameters are
selected by setting bits SSC4 to SSC0 in the S2D0 register, and the signals input to pins SCLMM and
SDAMM meet all three conditions (SCLMM release time, setup time, and hold time) listed in Table
25.14.
The BB bit in the S10 register becomes 1 when a start condition is detected, and becomes 0 when a
stop condition is detected. The set timing and reset timing of the BB bit depends on whether the mode
is standard mode or fast-mode. Refer to the BB bit set/reset times in Table 25.15.
Table 25.15 lists the Recommended Values of Bits SSC4 to SSC0 in Standard Clock Mode.
BB bit in the S10 register
TRX bit in the S10 register
Bits BC2 to BC0 in the S1D0 register
Figure 25.13 Start Condition Detection
BB bit in the S10 register
TRX bit in the S10 register
MST bit in the S10 register
Bits BC2 to BC0 in the S1D0 register
Figure 25.14 Stop Condition Detection
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
SCLMM
SDAMM
Setup
SCLMM
SDAMM
Setup
25. Multi-master I
SCLMM open
Hold
Setting BB bit
SCLMM open
Hold
Resetting BB bit
0.5 fVIIC cycles
2
C-bus Interface
(In slave mode)
000b
000b
Page 569 of 807
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