Renesas M16C/64C User Manual page 790

M16C/64C Group
Memory Expansion Mode and Microprocessor Mode
(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus )
Read timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
RD
Write timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
WR, WRL,
WRH
WR , WRL ,
1
t =
cyc
f
(BCLK)
Measuring conditions
V = V
CC1 CC2
Input timing voltage: V = 0.6 V, V
Output timing voltage: V = 1.5 V, V
Figure 31.30 Timing Diagram
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
t
d(BCLK-CS)
50ns(max.)
t
t
d(AD-ALE)
h(ALE-AD)
(0.5 × t -40ns(min.)
cyc (0.5 × t -15ns(min.)
cyc
Address
t
d(AD-RD)
t
d(BCLK-AD)
0ns(min.)
50ns(max.)
t
d(BCLK-ALE)
t
h(BCLK-ALE)
25ns(max.)
-4ns(min.)
t
d(BCLK-CS)
50ns(max.)
Address
t
d(AD-ALE)
(0.5 × t -40ns(min.)
cyc
t
d(BCLK-AD)
50ns(max.)
t t
d(BCLK-ALE) h(BCLK-ALE)
25ns(max.)
-4ns(min.)
= 3V
= 2.4 V
IL IH
= 1.5 V
OL OH
t
cyc
t
dz(RD-AD)
8ns(max.)
t
ac3(RD-DB)
{(n-0.5) × t -60}ns(max.)
cyc
t
d(BCLK-RD)
40ns(max.)
t
cyc
t
d(BCLK-DB)
50ns(max.)
Data output
t
d(DB-WR)
{(n-0.5) × t -50}ns(min.)
cyc
t
d(AD-WR)
0ns(min.)
t
d(BCLK-WR)
40ns(max.)
n: 2 (when 2 waits)
3 (when 3 waits)
31. Electrical Characteristics
V = V = 3V
CC1 CC2
t
h(BCLK-CS)
t 0ns(min.)
h(RD-CS)
(0.5 × t -10)ns(min.)
cyc
Address
Data input
t
h(RD-DB)
t
su(DB-RD)
0ns(min.)
60ns(min.)
t
h(BCLK-AD)
0ns(min.)
t
h(RD-AD)
(0.5 × t -10)ns(min.)
cyc
t
h(BCLK-RD)
0ns(min.)
t
h(BCLK-CS)
t
h(WR-CS)
0ns(min.)
(0.5 × t -10)ns(min.)
cyc
Address
t
h(WR-DB)
(0.5 × t -25)ns(min.)
cyc
t
h(BCLK-AD)
0ns(min.)
t
h(WR-AD)
(0.5 × t -15)ns(min.)
cyc
t
h(BCLK-WR)
0ns(min.)
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