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M16C/64C Group
DRFLG (Data receiving flag) (b2)
The DRFLG bit indicates the receiving state of the remote control signal. The bit is 1 while receiving
one frame. When data reception ends, the bit becomes 0.
Conditions to become 0:
•
The EN bit in the PMCiCON0 register is 0 (PMCi operation disabled).
•
The counter value is larger than values of registers PMCiHDPMAX, PMCiD0PMAX, and
PMCiD1PMAX (if the counter value is larger than these register values, this bit becomes 0 after
waiting one to two cycles of the count source).
Conditions to become 1:
The condition to become 1 is dependent on bits TYP1 to TYP0 in the PMCiCON1 register (receive
mode select).
•
When bits TYP1 to TYP0 are 00b (pulse period measurement) or 01b (high level width
measurement):
rising edge of the PMCi internal input signal
•
When bits TYP1 to TYP0 are 10b (pulse width measurement):
rising edge and falling edge of the PMCi internal input signal
BFULFLG (Receive buffer full flag) (b3)
Conditions to become 0:
•
The EN bit in the PMCiCON0 register is 0 (PMCi operation disabled).
•
The DRFLG bit in the PMCiSTS register changes from 0 to 1.
•
The value of the PMC0RBIT register changes from 48 to 1.
Condition to become 1:
•
The value of the PMC0RBIT register changes from 47 to 48.
PTHDFLG (Header pattern match flag) (b4),
PTD0FLG (Data 0 pattern match flag) (b5),
PTD1FLG (Data 1 pattern match flag) (b6),
SDFLG (Special pattern match flag) (b7)
Conditions to become 0:
•
The EN in the PMCiCON0 register bit is 0 (PMCi stops).
•
The DRFLG bit in the PMCiSTS register changes from 0 to 1.
•
See Table 22.7 "Measurements and Flags".
•
The REFLG bit changes from 0 to 1.
Condition to become 1:
•
See Table 22.7 "Measurements and Flags".
Table 22.7
Measurements and Flags
Value (Measurements) of the PMCiTIM Register
Between PMCiHDPMIN and PMCiHDPMAX
(header measurement in PMCi)
Between PMCiD0PMIN and PMCiD0PMAX
Between PMCiD1PMIN and PMCiD1PMAX
Between PMCiHDPMIN and PMCiHDPMAX
(special data measurement in PMCi)
Values not listed above
Note:
1.
When the HDEN bit in the PMCiCON0 register is 1 (header enabled), PTD0FLG, PTD1FLG, and
SDFLG remain unchanged until header is detected.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
22. Remote Control Signal Receiver
Flag
PTHDFLG
PTD0FLG
1
0
(1)
0
1
0
0
0
0
0
0
PTD1FLG
SDFLG
0
0
0
0
(1)
0
1
(1)
0
1
0
0
Page 416 of 807
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