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M16C/64C Group
2
In I
C mode, functions and timings vary depending on the IICM2 bit setting in the UiSMR2 register.
Figure 23.20 shows Transfer to UiRB Register and Interrupt Timing. See Figure 23.20 for the timing
of transferring data to the UiRB register, the bit position of the data stored in the UiRB register, types
of interrupts, interrupt requests, and DMA request generation timing.
Table 23.18 lists a comparison of other functions in clock synchronous serial I/O mode with I
2
Table 23.18
I
C Mode Functions
Function
Start and stop
condition detect
(3)
interrupts
Transmission, NACK
(2, 3)
interrupt
Reception, ACK
(2, 3)
interrupt
Timing for transferring
data from UART
reception shift register
to UiRB register
UARTi transmission
output delay
Read RXDi and SCLi
pin levels
Initial value of TXDi
and SDAi outputs
Initial and end values
of SCLi
DMA1, DMA3 factor
(2)
Read received data
i = 0 to 2, 5 to 7
SMD2 to SMD0: Bits in the UiMR register
CKPOL: Bit in the UiC0 register
IICM: Bit in the UiSMR register
IICM2: Bit in the UiSMR2 register
CKPH: Bit in the UiSMR3 register
UiIRS: Bit in the UCON or UiC1 register
Notes:
1.
Set the initial value of SDAi output while bits SMD2 to SMD0 in the UiMR register are 000b (serial interface
disabled).
2.
See Figure 23.20 "Transfer to UiRB Register and Interrupt Timing".
3.
The procedure to change interrupt sources is as follows:
(1) Disable the interrupt to be changed the source.
(2) Change the source of interrupt.
(3) Set the IR bit in the interrupt control register of that interrupt to 0 (no interrupt requested).
(4) Set bits ILVL2 to ILVL0 in the interrupt control register of that interrupt.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Clock Synchronous Serial
I/O Mode (SMD2 to SMD0
= 001b, IICM = 0 )
-
UARTi transmission
Transmission started or
completed (selected by
UiIRS)
UARTi reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Not delayed
Possible when the
corresponding port
direction bit = 0
CKPOL = 0 (high)
CKPOL = 1 (low)
-
UARTi reception
1st to 8th bits of the
received data are stored
in bits 0 to 7 in the UiRB
register.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
2
I
C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0
(NACK/ACK interrupt)
CKPH = 1 (Clock delay)
Start condition or stop condition detection
(See Figure 23.22 "STSPSEL Bit Functions")
No acknowledgment
detection (NACK)
Rising edge of the 9th bit of SCLi
Acknowledgment detection (ACK)
Rising edge of the 9th bit of SCLi
Rising edge of the 9th bit of SCLi
Delayed
Always possible no matter how
the corresponding port direction
bit is set
The value set in the port register
2
(1)
before setting I
C mode
Low
Acknowledgment detection (ACK)
1st to 8th bits of the received data
are stored in bits 7 to 0 in the
UiRB register.
2
C mode.
IICM2 = 1
(UART transmit/receive interrupt)
CKPH = 1 (Clock delay)
UARTi transmission
Falling edge of the 9th bit of SCLi
UARTi reception
Falling edge of the 9th bit of SCLi
Falling edges of the 8th bit of
SCLi and rising edges of the 9th
bit of SCLi
Delayed
Always possible no matter how
the corresponding port direction
bit is set
The value set in the port register
2
(1)
before setting I
C mode
Low
UARTi reception
Falling edge of the 9th bit of SCLi
Refer to Figure 23.20 "Transfer to
UiRB Register and Interrupt
Timing".
Page 492 of 807
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