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M16C/64C Group
EHOLD (Error flag hold bit) (b3)
When a receive error occurs, the period when the REFLG bit in the PMC0STS register retains 1
(receive error) can be selected. Refer to "REFLG (Receive error flag) (b1)" in 22.2.5 "PMCi Status
Register (PMCiSTS) (i = 0, 1)" for details.
HDEN (Header pattern enable bit) (b4)
While the HDEN bit is 1 (header enabled), after data reception starts (DRFLG flag is 1), if data 0, data
1, or special data is detected before the header is detected, the following occur:
•
The REFLG bit in the PMCiSTS register becomes 1 (error occurs)
•
Bits PTD0FLG, PTD1FLG, and SDFLG in the PMCiSTS register remain unchanged.
•
Registers PMC0DAT0 to PMC0DAT5 are not rewritten.
DRINT1-DRINT0 (Receive interrupt control bit) (b7-b6)
Set these bits to select a condition for generating a data reception complete interrupt request.
Set the DRINT bit in the PMC0INT register to 1 (reception complete interrupt enabled) after setting
these bits.
When setting the DRINT1 bit to 1, set the EHOLD bit in the PMC0CON0 register to 1 (hold the REFLG
bit state after next data received).
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
22. Remote Control Signal Receiver
Page 408 of 807
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