Registers - Renesas M16C/64C User Manual

M16C/64C Group
Table 8.2 I/O Pins
Pin Name
XIN
XOUT
XCIN
XCOUT
CLKOUT
BCLK
Note:
1. Set the port direction bits which share pins to 0 (input mode).
8.2

Registers

Table 8.3 Registers
Address
0004h Processor Mode Register 0
0006h System Clock Control Register 0
0007h System Clock Control Register 1
000Ch Oscillation Stop Detection Register
0012h Peripheral Clock Select Register
0016h Peripheral Clock Stop Register 1
001Ch PLL Control Register 0
001Eh Processor Mode Register 2
Note:
1. Bits CM20, CM21, and CM27 remain unchanged at oscillator stop detect reset.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
I/O
Input
I/O pins for the main clock oscillator
Output
(1)
Input
I/O pins for a sub clock oscillator
(1)
Output
Output Clock output (in single-chip mode)
Output BCLK output (in memory expansion and microprocessor modes)
Register
Function
Symbol
(CNVSS pin is low)
PM0
(CNVSS pin is high)
CM0
CM1
CM2
0X00 0010b
PCLKR
PCLKSTP1 0XXX XX00b
PLC0 0X01 X010b
PM2 XX00 0X01b
8. Clock Generator
Reset Value
0000 0000b
0000 0011b
0100 1000b
0010 0000b
(1)
0000 0011b
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