Count Source Protection Mode Register (Cspr) - Renesas M16C/64C User Manual

M16C/64C Group
VW2C3 (WDT detection flag) (b3)
Use this bit in an interrupt routine to determine the source of the interrupts from the watchdog timer, the
oscillator stop/restart detect, the voltage monitor 1, and the voltage monitor 2.
Condition to become 0:
•
Writing 0 by a program
Condition to become 1:
•
Watchdog timer underflow detected
(This flag remains unchanged even if 1 is written by a program.)
15.2.2

Count Source Protection Mode Register (CSPR)

Count Source Protection Mode Register
b7 b6 b5 b4 b3 b2 b1
CSPRO (Count source protection mode select bit) (b7)
Select the CSPRO bit before the watchdog timer starts counting. Once counting starts, do not change
the CSPRO bit.
Condition to become 0:
•
Reset when the CSPROINI bit in the OFS1 address is 1.
(This flag remains unchanged even if 0 is written by a program.)
Conditions to become 1:
•
When the CSPROINI bit in the OFS1 address is 0
•
Write 0, and then write 1.
Make sure no interrupts or DMA transfers occur between setting the bit to 0 and setting it to 1.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Symbol
b0
CSPR
Bit Symbol Bit Name
—
No register bits. If necessary, set to 0. The read value is 0.
(b6-b0)
Count source protection mode
CSPRO
select bit
Address
037Ch 0000 0000b
(when the CSPROINI bit in the OFS1 address is 1)
1000 0000b
(when the CSPROINI bit in the OFS1 address is 0)
0 : Count source protection mode
disabled
1 : Count source protection mode enabled
15. Watchdog Timer
Reset Value
Function RW
RW
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