Renesas M16C/64C User Manual page 523

M16C/64C Group
Table 23.16 Registers Used and Settings in I
Register Bits
PCLKR PCLK1
PCLKSTP1 PCKSTP1A Set to 0 when using f1.
0 to 7
UiTB
8
0 to 7
8
UiRB ABT
OER
13 to 15
UiBRG 0 to 7
SMD2 to
SMD0
CKDIR
UiMR
4 to 6
IOPOL
CLK1, CLK0
CRS
TXEPT
UiC0
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
UiC1
UjIRS
UjRRM,
UiLCH,
UiERE
IICM
ABC
UiSMR
BBS
3 to 7
i = 0 to 2, 5 to 7; j = 2, 5 to 7
Notes:
1. This table does not describe a procedure.
2. The TXD2 pin is N-channel open drain output. Nothing is assigned to the NCH bit in the U2C0 register. If
necessary, set it to 0.
3. When using UART1 in I
U1C0 register to 0 ( CTS / RTS enabled) and the CRS bit to 0 ( CTS input).
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Master
Select the count source for the UiBRG
register.
When transmitting, set the transmission
data. When receiving, set FFh.
When transmitting, set to 1. When
receiving, set the value in the ACK bit.
Reception data can be read.
ACK or NACK is set in this bit.
Arbitration lost detection flag
Overrun error flag
When read, the read value is undefined.
Set a bit rate.
Set to 010b.
Set to 0.
Set to 0.
Set to 0.
Select the count source for the UiBRG
register.
Disabled because CRD is 1
Transmit register empty flag
(3)
Set to 1.
(2)
Set to 1.
Set to 0.
Set to 1.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Reception complete flag
Set to 1.
Set to 0.
Set to 1.
Select the timing that arbitration lost is
detected.
Bus busy flag
Set to 0.
C mode, to enable the CTS / RTS separate function of UART0, set the CRD bit in the
2
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
2 (1)
C Mode (1/2)
Function
Select the count source for the UiBRG
register.
Set to 0 when using f1.
When transmitting, set the transmission
data. When receiving, set FFh.
When transmitting, set to 1. When receiving,
set the value in the ACK bit.
Reception data can be read.
ACK or NACK is set in this bit.
Disabled
Overrun error flag
When read, the read value is undefined.
Disabled
Set to 010b.
Set to 1.
Set to 0.
Set to 0.
Disabled
Disabled because CRD is 1
Transmit register empty flag
Set to 1.
Set to 1.
Set to 0.
Set to 1.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Reception complete flag
Set to 1.
Set to 0.
Set to 1.
Disabled
Bus busy flag
Set to 0.
Slave
(2)
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