Renesas M16C/64C User Manual page 639

M16C/64C Group
26.3.5.5 Reception Examples
Figure 26.10 shows a Reception Example and Figure 26.11 shows a Reception Example (Change
from Error Low Pulse Output Disabled to Enabled When an Error Occurs).
When a receive error occurs, the CRERRFLG bit in the CECFLG register becomes 1 (receive error).
If a reception ends due to the error during reception, set the CRXDEN bit in the CECC3 register to 0
(receive disabled). When the CRXDEN bit is set to 0, the CRERRFLG bit becomes 0. To restart
reception, set the CRXDEN bit to 0 (reception disabled), and then set the CRXDEN bit to 1 (reception
enabled) after waiting for one or more cycles of the count source.
CEC
CRXDEN bit
CRFLG bit
CRSTFLG bit
CRD8FLG bit
IR bit
CCRB1 register
CCRBE bit
CCRBAI bit
CRXDEN bit: Bit in the CECC3 register
Bits CRFLG, CRD8FLG, and CRSTFLG: Bits in the CECFLG register
IR bit: Bit in the CEC2IC register
Bits CCRBE and CCRBAI: Bits in the CCRB2 register
The above diagram applies under the following conditions.
The CFIL bit in the CICC2 register is set to 0 (filter disabled).
The CRISEL0 bit in the CISEL register is set to 0 (8th bit receive interrupt disabled).
The CRISEL1 bit in the CISEL register is set to 1 (10th bit receive interrupt enabled).
The CRISELS bit in the CISEL register is set to 1 (reception start bit interrupt enabled).
Figure 26.10 Reception Example
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Header block
. . . .
ST H7 H6 H1
Set to 0 by acceptance of an
interrupt request or by a program
Undefined
Undefined
Undefined
26. Consumer Electronics Control (CEC) Function
H0 EOM ACK D7 D6
Header block data
Data block
. . . .
D1 D0 EOM ACK
Set to 0 by acceptance of an
interrupt request or by a program
Data block data
Header block EOM
Data block EOM
Header block ACK
Data block ACK
Page 606 of 807