Flash Memory Control Register 1 (Fmr1) - Renesas M16C/64C User Manual

M16C/64C Group
30.3.2

Flash Memory Control Register 1 (FMR1)

Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1
0
FMR11 (Write to FMR6 register enable bit) (b1)
Change FMR11 bit when the PM24 bit in the PM2 register is 0 ( NMI interrupt disabled) or high is input
to the NMI pin.
FMR16 (Lock bit status flag) (b6)
This bit indicates the execution result of the read lock bit status command.
FMR17 (Data flash wait bit) (b7)
This bit is used to select the number of waits for data flash.
When setting this bit to 0, one wait is inserted to the read cycle of the data flash. The write cycle is not
affected.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
b0
Symbol
FMR1
Bit Symbol Bit Name
—
Reserved bit
(b0)
Write to FMR6 register
FMR11
enable bit
—
Reserved bits
(b3-b2)
—
Reserved bit
(b4)
—
No register bit. If necessary, set to 0. The read value is undefined.
(b5)
Lock bit status flag
FMR16
Data flash wait bit
FMR17
Address
0221h
Function
The read value is undefined.
0 : Disabled
1 : Enabled
The read value is undefined.
Set to 0
0 : Lock
1 : Unlock
0 : 1 wait
1 : Follow the setting of the PM17 bit in the
PM1 register
30. Flash Memory
Reset Value
00X0 XX0Xb
RW
RO
RW
RO
RW
—
RO
RW
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