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M16C/64C Group
26.3.5.2
Data Bit Detection
The detect timing of the start bit and data bit (other than the start bit) is selected by setting the
CRRNG bit in the CECC2 register. Select the data bit acceptable range by setting the CDATRNG bit
in the CECC2 register. Figure 26.6 shows Data Bit Acceptable Range (CRRNG Bit = 0).
When the CRRNG bit is 0 (detects falling edge acceptable range), the input data is determined as
data 1 if the rising edge is detected before 1.05 ms and the input data is determined as data 0 if the
rising edge is detected after 1.05 ms.
CEC input
(input data: 0)
CEC input
(input data: 1)
Figure 26.6
Data Bit Acceptable Range (CRRNG Bit = 0)
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
0 ms
Determined as data 1 before 1.05 ms
0 ms
CRRNG and CDATRNG: Bits in the CECC2 register.
26. Consumer Electronics Control (CEC) Function
Only a falling edge is detected
Acceptable range
When the CDATRNG bit is 0: ±350 µs
When the CDATRNG bit is 1: ±500 µs
Determined as
data 0 after 1.05 ms
1.05 ms
Only a falling edge is detected
Acceptable range
When the CDATRNG bit is 0: ±350 µs
When the CDATRNG bit is 1: ±500 µs
1.05 ms
2.4 ms
2.4 ms
Page 601 of 807
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