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M16C/64C Group
CEFLG (Counter overflow flag) (b4)
Conditions to become 0:
•
The EN bit in the PMCiCON0 register is 0 (PMCi operation stops)
•
Measurement timing selected by bits TYP1 to TYP0 in the PMCiCON1 register
Condition to become 1:
•
Counter overflow (the counter becomes 0000h from FFFFh)
PSEL1-PSEL0 (Input pin select bit) (b7-b6)
Change these bits when the EN bit in the PMCiCON0 register and the ENFLG bit in the PMCiCON2
register are both 0 (PMCi stops).
Refer to Figure 22.2 "Remote Control Signal Receiver Block Diagram (2/3) (PMCi Input)" and 22.3.1.2
"PMCi Input".
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
22. Remote Control Signal Receiver
Page 412 of 807
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