Peripheral Clock Select Register (Pclkr); Oi Transmit/Receive Register (Sitrr) (I = 3, 4) - Renesas M16C/64C User Manual

M16C/64C Group
24.2.1

Peripheral Clock Select Register (PCLKR)

Peripheral Clock Select Register
b7 b6 b5 b4 b3 b2 b1
0 0 0 0 0
Rewrite the PCLKR register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
24.2.2 SI/Oi Transmit/Receive Register (SiTRR) (i = 3, 4)
SI/Oi Transmit/Receive Register (i = 3, 4)
b7
Write to the SiTRR register while the serial interface is neither transmitting nor receiving.
Write a value to the SiTRR register each time 1-byte data is received, even when data is only received.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
b0 Symbol
PCLKR
Bit Symbol Bit Name
Timers A and B clock select bit
(clock source for timers A and
PCLK0
B, the dead time timer, and
multi-master I
SI/O clock select bit
(clock source for UART0 to
PCLK1
UART2, UART5 to UART7,
SI/O3, and SI/O4)
—
Reserved bits
(b4-b2)
Clock output function
PCLK5 expansion bit
(enabled in single-chip mode)
—
Reserved bits
(b7-b6)
b0
Symbol
S3TRR
S4TRR
Transmission/reception starts by writing transmit data to this register.
After transmission/reception completes, receive data can be read.
Address
0012h
0: f2TIMAB/f2IIC
1: f1TIMAB/f1IIC
2
C-bus interface)
0: f2SIO
1: f1SIO
Set to 0
0: Selected by setting bits CM01 to CM00
in the CM0 register
1: Output f1
Set to 0
Address
0270h
0274h
Function
24. Serial Interface SI/O3 and SI/O4
Reset Value
0000 0011b
Function
Reset Value
Undefined
Undefined
Page 523 of 807
RW
RW
RW
RW
RW
RW
RW
RW