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M16C/64C Group
11.3.5.4
Read and Write Signals
When the data bus is 16 bits wide, the read and write signals can be selected based on combinations
of RD , BHE , and WR , or combinations of RD , WRL , and WRH using the PM02 bit in the PM0 register.
When the data bus is 8 bits wide, use combinations of RD , WR , and BHE .
Table 11.6 lists Operation of the RD , WRL and WRH Signals. Table 11.7 lists Operation of the RD ,
WR and BHE Signals.
Operation of the RD, WRL and WRH Signals
Table 11.6
Data Bus Width
16-bit
(BYTE pin input = low)
Operation of the RD, WR and BHE Signals
Table 11.7
Data Bus
RD
Width
16-bit
(BYTE pin
input = low)
8-bit
(BYTE pin
input = high)
Note:
1.
Do not use.
11.3.5.5
ALE Signal
The ALE signal is used to latch the address when a multiplexed bus space is accessed. Latch the
address at the falling edge of the ALE signal.
When BYTE pin input is high
ALE
A0/D0 to A7/D7
When bits PM05 to PM04 in the PM0 register are 01b or 10b (the multiplexed bus is either the CS2 or CS1 area)
A8 to A19
When bits PM05 to PM04 in the PM0 register are 11b (the entire CS area is the multiplexed bus)
A8
Figure 11.3
ALE Signal, Address Bus, and Data Bus
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
RD
WRL
L
H
H
L
H
H
H
L
WR
BHE
H
L
L
L
H
L
H
L
H
L
H
H
H
L
L
L
H
L
−
(1)
H
L
−
(1)
L
H
Address
Data
Address
Address
WRH
Status of External Data Bus
H
Read data
H
Write 1 byte of data to an even address
L
Write 1 byte of data to an odd address
L
Write data to both even and odd addresses
A0
Status of External Data Bus
H
Write 1 byte of data to an odd address.
H
Read 1 byte of data from an odd address.
L
Write 1 byte of data to an even address.
L
Read 1 byte of data from an even address.
L
Write data to both even and odd addresses.
L
Read data from both even and odd addresses.
H or L Write 1 byte of data.
H or L Read 1 byte of data.
When BYTE pin input is low
ALE
A0
A1/D0 to A8/D7
A9 to A19
Address
Address
Data
Address
Page 146 of 807
11. Bus
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