Table of Contents
Advertisement
M16C/64C Group
FER (Framing error flag) (b13)
The FER bit is disabled when bits SMD2 to SMD0 are set to 001b (clock synchronous serial I/O mode)
2
or to 010b (I
C mode). The read value is undefined.
Conditions to become 0:
•
Bits SMD2 to SMD0 in the UiMR register are 000b (serial interface disabled).
•
The RE bit in the UiC1 register is 0 (reception disabled).
•
The lower bytes of the UiRB register are read.
Condition to become 1:
•
The set number of stop bits is not detected.
(detected when the received data is transferred from the UARTi receive register to the UiRB
register.)
PER (Parity error flag) (b14)
The PER bit is disabled when bits SMD2 to SMD0 are set to 001b (clock synchronous serial I/O mode)
2
or to 010b (I
C mode). The read value is undefined.
Conditions to become 0:
•
Bits SMD2 to SMD0 in the UiMR register are 000b (serial interface disabled).
•
The RE bit in the UiC1 register is 0 (reception disabled).
•
The lower bytes of the UiRB register are read.
Condition to become 1:
•
The number of 1's of the parity bit and character bits do not match the set value of the PRY bit in
the UiMR register.
(detected when the received data is transferred from the UARTi receive register to the UiRB
register.)
SUM (Error sum flag) (b15)
The SUM bit is disabled when bits SMD2 to SMD0 are set to 001b (clock synchronous serial I/O mode)
2
or to 010b (I
C mode). The read value is undefined.
Conditions to become 0:
•
Bits SMD2 to SMD0 in the UiMR register are 000b (serial interface disabled).
•
The RE bit in the UiC1 register is 0 (reception disabled).
•
Bits PER, FER and OER are all 0 (no error).
Condition to become 1:
•
At least two bits out of PER, FER, or OER are 1 (error found).
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Page 464 of 807
Advertisement
Table of Contents
