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M16C/64C Group
RXDi
RXD data
inverse circuit
STPS
1SP
0
SP
SP
1
2SP
0
STPS
2SP
1
SP
SP
0
1SP
SP: Stop bit
PAR: Parity bit
i = 0 to 2, 5 to 7
SMD2 to SMD0, STPS, PRYE, IOPOL: Bits in the UiMR register
UiERE: Bit in the UiC1 register
Figure 23.4
UARTi Transmit/Receive Unit Block Diagram
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
IOPOL
Not inverted
0
1
Inverted
2
I
C
PRYE
clock sync
PAR
type
disabled
0
0
PAR
1
1
PAR enabled
UART
SMD2 to SMD0
0
0
0
0
0
PRYE
SMD2 to SMD0
PAR enabled
UART
1
1
PAR
0
0
2
I
C
PAR
clock sync
disabled
type
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Clock sync type
UART
(7 bits)
UART
(8 bits)
UART (7 bits)
0
0
1
1
2
2
I
C
I
C
UART
clock sync type
(9 bits)
UART
(8 bits)
UART
(9 bits)
0
D8
D7 D6 D5 D4 D3 D2 D1 D0
Logic reverse circuit + MSB/LSB conversion circuit
Logic inverse circuit + MSB/LSB conversion circuit
Data bus
Logic inverse circuit + MSB / LSB conversion circuit
D8
D7 D6 D5 D4 D3 D2 D1 D0
UART
(8 bits)
UART
(9 bits)
2
2
I
C
I
C
UART
clock sync type
(9 bits)
1
1
0
0
UART (7 bits)
UART
(7 bits)
UART
(8 bits)
Error signal output disabled
Clock sync type
0
1
UiERE
Error signal output enabled
UARTi receive register
UARTi transmit register
IOPOL
Not inverted
0
TXD data
Error signal
inverse
output
1
circuit
circuit
Inverted
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UiRB
register
UiTB
register
TXDi
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