Operating Speed; Data Protect Function - Renesas M16C/64C User Manual

M16C/64C Group
30.8.3

Operating Speed

Select a CPU clock frequency of 10 MHz or less by setting the CM06 bit in the CM0 register and bits
CM17 and CM16 in the CM1 register before entering CPU rewrite mode (EW0 or EW1 mode). Also, set
the PM17 bit in the PM1 register to 1 (wait state).
30.8.4

Data Protect Function

Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02
bit to 0 (lock bit enabled). The lock bit allows blocks to be individually protected (locked) against being
programmed and erased. This prevents data from being inadvertently written to or erased from the
flash memory. Table 30.14 lists Lock Bit and Block State.
Table 30.14 Lock Bit and Block State
FMR02 Bit in the
FMR0 Register
0 (enabled)
1 (disabled)
Condition to become 0:
• Execute the lock bit program command
Condition to become 1:
• Execute the block erase command while the FMR02 bit in the FMR0 register is set to 1 (lock bit
disabled).
If the block erase command is executed while the FMR02 bit is set to 1, the target block is erased
regardless of lock bit status. The lock bit data can be read by the read lock bit status command.
Refer to 30.8.6 "Software Commands", for details on each command.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Lock Bit
0 (locked) Protected against being programmed and erased
1 (unlocked) Can be programmed or erased
0 (locked)
Can be programmed or erased
1 (unlocked)
Block State
30. Flash Memory
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