Renesas M16C/64C User Manual page 469

M16C/64C Group
22.3.3.1 Setting Procedure
To start or stop counting, follow these steps:
(1) Set bits CSRC1 to CSRC0 and bits CDIV1 to CDIV0 in the PMCiCON3 register.
(2) Set bits PSEL1 to PSEL0 in the PMCiCON2 register and bits FIL and SINV in the PMCiCON0
register.
(3) Wait for four cycles of count source.
(4) Set the EN bit in the PMC1CON0 register to 1 (0 to stop).
(5) Set the EN bit in the PMC0CON0 register to 1 (0 to stop).
(6) Wait for two cycles of count source.
(7) Confirm that the ENFLG bit in the PMC0CON2 register is 1 (0 to stop). (The ENFLG bit in the
PMC1CON2 register is disabled)
22.3.3.2 Header and Special Data Detection
The header and special data can be detected. Table 22.15 lists Selection of Header and Special Data
Detecting Block.
Table 22.15 Selection of Header and Special Data Detecting Block
Detected Item
PMC0 PMC1
- Header
- Special data
Header Special data
Special data Header
-: Neither header nor special data is detected
Note:
1. Only set the values listed in this table.
When the header is enabled, after data reception starts (DRFLG flag is 1), if data 0, data 1, or special
data is detected before the header is detected, the following occur:
•
The REFLG bit in the PMC0STS register becomes 1 (error occurs).
•
Bits PTD0FLG, PTD1FLG, and SDFLG in the PMC0STS register remain unchanged.
•
Registers PMC0DAT0 to PMC0DAT5 remain unchanged.
22.3.3.3 Status Flag and Interrupt
When connecting PMC0 and PMC1, use flags and the interrupt control in PMC0. The corresponding
bits are as follows:
Each bit in the PMC0STS register
Each bit in the PMC0INT register
The INFLG bit in the PMC0CON2 register
Even when detecting the header or special data in PMC1, the result including that data can be
detected in the above registers.
22.3.3.4 Receive Data Buffer (PMC0)
There is a 6-byte (48-bit) buffer for storing received data. When the data exceeds 48 bits, the buffer is
sequentially overwritten from the first bit. Refer to 22.2.11 "PMC0 Receive Data Store Register i
(PMC0DATi) (i = 0 to 5)" and 22.2.10 "PMC0 Receive Bit Count Register (PMC0RBIT)".
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
PMC0CON0 register
HDEN bit SDEN bit
1 0
0 1
1 1
1 1
22. Remote Control Signal Receiver
(1)
Bit Setting
PMC0CON1 register
EXHDEN bit
1
0
0
1
EXSDEN bit
0
1
1
0
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