33.15.15 Otg Host Periodic Transmit Fifo Size Register; (Otg_Hptxfsiz); Otg Device In Endpoint Transmit Fifo Size Register (Otg_Dieptxfx); Fifo Number) - ST STM32F423 Reference Manual

Advanced arm-based 32-bit mcus
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USB on-the-go full-speed (OTG_FS)

33.15.15 OTG host periodic transmit FIFO size register

(OTG_HPTXFSIZ)

Address offset: 0x100
Reset value: 0x0200 0400
31
30
29
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rw
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15
14
13
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Bits 31:16 PTXFSIZ[15:0]: Host periodic Tx FIFO depth
This value is in terms of 32-bit words.
Minimum value is 16
Bits 15:0 PTXSA[15:0]: Host periodic Tx FIFO start address
This field configures the memory start address for periodic transmit FIFO RAM.
33.15.16 OTG device IN endpoint transmit FIFO size register
(OTG_DIEPTXFx) (x = 1..5, where x is the

FIFO number)

Address offset: 0x104 + (x – 1) * 0x04
Reset value: 0x0200 0200 + (x * 0x200)
31
30
29
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15
14
13
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Bits 31:16 INEPTXFD[15:0]: IN endpoint Tx FIFO depth
Bits 15:0 INEPTXSA[15:0]: IN endpoint FIFOx transmit RAM start address
1188/1324
28
27
26
25
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rw
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12
11
10
9
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28
27
26
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12
11
10
9
rw
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This value is in terms of 32-bit words.
Minimum value is 16
This field contains the memory start address for IN endpoint transmit FIFOx. The address
must be aligned with a 32-bit memory location.
24
23
22
PTXFSIZ[15:0]
rw
rw
rw
8
7
6
PTXSA[15:0]
rw
rw
rw
24
23
22
INEPTXFD[15:0]
rw
rw
rw
8
7
6
INEPTXSA[15:0]
rw
rw
rw
RM0430 Rev 8
21
20
19
18
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rw
rw
5
4
3
2
rw
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21
20
19
18
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5
4
3
2
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RM0430
17
16
rw
rw
1
0
rw
rw
17
16
rw
rw
1
0
rw
rw

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