Sai Xstatus Register (Sai_Xsr) Where X Is A Or B - ST STM32F423 Reference Manual

RM0430
30.17.6

SAI xStatus register (SAI_xSR) where x is A or B

Address offset: block A: 0x018
Address offset: block B: 0x038
Reset value: 0x0000 0008
31 30 29 28
15 14 13 12
Bits 31:19 Reserved, always read as 0.
Bits 18:16 FLTH: FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by
hardware and its setting depends on SAI block configuration (transmitter or receiver mode).
If SAI block is configured as transmitter:
000: FIFO_empty
001: FIFO <= ¼ but not empty
010: ¼ < FIFO <= ½
011: ½ < FIFO <= ¾
100: ¾ < FIFO but not full
101: FIFO full
If SAI block is configured as receiver:
000: FIFO_empty
001: FIFO < ¼ but not empty
010: ¼ <= FIFO < ½
011: ½ =< FIFO < ¾
100: ¾ =< FIFO but not full
101: FIFO full
Bits 15:7 Reserved, always read as 0.
Bit 6 LFSDET: Late frame synchronization detection. This bit is read only.
0: No error.
1: Frame synchronization signal is not present at the right time.
This flag can be set only if the audio block is configured in Slave mode.
It is not used in AC'97 mode.
It may generate an interrupt if bit LFSDETIE in the SAI_xIM register is set.
This flag is cleared when the software sets bit CLFSDET in the SAI_xCLRFR register
Bit 5 AFSDET: Anticipated frame synchronization detection. This bit is read only.
0: No error.
1: Frame synchronization signal is detected earlier than expected.
This flag can be set only if the audio block is configured in Slave mode.
It is not used in AC'97.
It may generate an interrupt if bit AFSDETIE in the SAI_xIM register is set.
This flag is cleared when the software sets bit CAFSDET in the SAI_xCLRFR register
27 26 25 24
Reserved
11 10 9 8
Reserved
23 22 21
7 6 5
LFSDET AFSDET CNRDY
r r
RM0430 Rev 8
Serial audio interface (SAI)
20 19 18
r
4 3 2
FREQ WCKCFG
r r r
17 16
FLTH
r r
1 0
MUTED
OVRUDR
ET
r r
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