Otg Device In Endpoint X Interrupt Register (Otg_Diepintx); (X = 0 - ST STM32F423 Reference Manual

USB on-the-go full-speed (OTG_FS)

33.15.42 OTG device IN endpoint x interrupt register (OTG_DIEPINTx)

(x = 0..5, where x = Endpoint number)
Address offset: 0x908 + (x * 0x20)
Reset value: 0x0000 0080
This register indicates the status of an endpoint with respect to USB- and AHB-related
events. It is shown in
endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set.
Before the application can read this register, it must first read the device all endpoints
interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x
interrupt register. The application must clear the appropriate bit in this register to clear the
corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. NAK Res.
rc_w1
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 NAK: NAK input
Bit 12 Reserved, must be kept at reset value.
Bit 11 PKTDRPSTS: Packet dropped status
Bit 10 Reserved, must be kept at reset value.
Bit 9 Reserved, must be kept at reset value.
Bit 8 TXFIFOUDRN: Transmit Fifo Underrun (TxfifoUndrn)
Bit 7 TXFE: Transmit FIFO empty
1214/1324
Figure 403. The application must read this register when the IN
28 27 26 25
Res. Res. Res.
12 11 10 9
PKTD
Res. Res.
RPSTS
rc_w1
The core generates this interrupt when a NAK is transmitted or received by the device. In
case of isochronous IN endpoints the interrupt gets generated when a zero length packet is
transmitted due to unavailability of data in the Tx FIFO.
This bit indicates to the application that an ISOC OUT packet has been dropped. This bit
does not have an associated mask bit and does not generate an interrupt.
The core generates this interrupt when it detects a transmit FIFO underrun condition for this
endpoint. Dependency: This interrupt is valid only when Thresholding is enabled
This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely
empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in
the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG).
24 23 22
Res. Res. Res.
8 7 6
TXFIF
IN
OUD TXFE
EPNE EPNM
RN
rc_w1 r r rc_w1
RM0430 Rev 8
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
IN
ITTXFE TOC Res.
rc_w1 rc_w1
RM0430
17 16
Res. Res.
1 0
EP
XFRC
DISD
rc_w1 rc_w1