Otg Core Id Register (Otg_Cid); Otg Core Lpm Configuration Register (Otg_Glpmcfg) - ST STM32F423 Reference Manual

USB on-the-go full-speed (OTG_FS)

33.15.13 OTG core ID register (OTG_CID)

Address offset: 0x03C
Reset value: 0x0000 2000
This is a register containing the Product ID as reset value.
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 PRODUCT_ID[31:0]: Product ID field

33.15.14 OTG core LPM configuration register (OTG_GLPMCFG)

Address offset: 0x54
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
BESL
15 14 13
SLP L1DS
LPMRSP[1:0]
STS
r r r
Bits 31:29 Reserved, must be kept at reset value.
Bit 28 ENBESL: Enable best effort service latency
Note: Only the updated behavior (described in LPM Errata) is considered in this document
Bits 27:25 LPMRCNTSTS[2:0]: LPM retry count status
Note: Accessible only in host mode.
1184/1324
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Application-programmable ID field.
28 27 26 25
EN
LPMRCNTSTS[2:0]
rw r r r
12 11 10 9
BESLTHRS[3:0]
EN
rw rw rw rw
This bit enables the BESL feature as defined in the LPM errata:
0:The core works as described in the following document:
USB 2.0 Link Power Management Addendum Engineering Change Notice to the USB 2.0
specification, July 16, 2007
1:The core works as described in the LPM Errata:
Errata for USB 2.0 ECN: Link Power Management (LPM) - 7/2007
and so the ENBESL bit should be set to '1' by application SW.
Number of LPM host retries still remaining to be transmitted for the current LPM sequence.
24 23 22
PRODUCT_ID[31:16]
rw rw rw
8 7 6
PRODUCT_ID[15:0]
rw rw rw
24 23 22
SND
LPMRCNT[2:0]
LPM
rs rw rw
8 7 6
L1SS REM
EN WAKE
rw rw rw/r
RM0430 Rev 8
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
LPMCHIDX[3:0]
rw rw rw rw
5 4 3 2
BESL[3:0]
rw/r rw/r rw/r rw/r
RM0430
17 16
rw rw
1 0
rw rw
17 16
L1RSM
OK
rw r
1 0
LPM LPM
ACK EN
rw rw