Behavior In Debug Mode; Bxcan Functional Description; Transmission Handling; Figure 384. Bxcan In Combined Mode - ST STM32F423 Reference Manual

RM0430
32.6

Behavior in debug mode

When the microcontroller enters the debug mode (Cortex
bxCAN continues to work normally or stops, depending on:
•
DBG_CAN1_STOP bit for CAN1, DBG_CAN2_STOP bit for CAN2 or
DBG_CAN3_STOP bit for CAN3 in the DBGMCU_APB1_FZ register
• the DBF bit in CAN_MCR. For more details, refer to
status
32.7

bxCAN functional description

32.7.1

Transmission handling

In order to transmit a message, the application must select one empty transmit mailbox, set
up the identifier, the data length code (DLC) and the data before requesting the transmission
by setting the corresponding TXRQ bit in the CAN_TIxR register. Once the mailbox has left
empty state, the software no longer has write access to the mailbox registers. Immediately
after the TXRQ bit has been set, the mailbox enters pending state and waits to become the
highest priority mailbox, see Transmit Priority. As soon as the mailbox has the highest
priority it will be scheduled for transmission. The transmission of the message of the
scheduled mailbox will start (enter transmit state) when the CAN bus becomes idle. Once
the mailbox has been successfully transmitted, it will become empty again. The hardware
indicates a successful transmission by setting the RQCP and TXOK bits in the CAN_TSR
register.
If the transmission fails, the cause is indicated by the ALST bit in the CAN_TSR register in
case of an Arbitration Lost, and/or the TERR bit, in case of transmission error detection.
Transmit priority
By identifier
When more than one transmit mailbox is pending, the transmission order is given by the
identifier of the message stored in the mailbox. The message with the lowest identifier value
has the highest priority according to the arbitration of the CAN protocol. If the identifier
values are equal, the lower mailbox number will be scheduled first.

Figure 384. bxCAN in combined mode

registers.
RM0430 Rev 8
Controller area network (bxCAN)
®
-M4 with FPU core halted), the
Section 32.9.2: CAN control and
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