33.15.11 Otg Non-Periodic Transmit Fifo/Queue Status Register; (Otg_Hnptxsts) - ST STM32F423 Reference Manual

RM0430
Device mode
Bits 31:16 TX0FD: Endpoint 0 Tx FIFO depth
This value is in terms of 32-bit words.
Minimum value is 16
Programmed values must respect the available FIFO memory allocation and must not
exceed the power-on value.
Bits 15:0 TX0FSA: Endpoint 0 transmit RAM start address
This field configures the memory start address for the endpoint 0 transmit FIFO RAM.

33.15.11 OTG non-periodic transmit FIFO/queue status register

(OTG_HNPTXSTS)

Address offset: 0x02C
Reset value: 0x0008 0200
Note: In device mode, this register is not valid.
This read-only register contains the free space information for the non-periodic Tx FIFO and
the non-periodic transmit request queue.
31 30 29
Res.
r r
15 14 13
r r r
28 27 26 25
NPTXQTOP[6:0]
r r r r
12 11 10 9
r r r r
USB on-the-go full-speed (OTG_FS)
24 23 22
r r r
8 7 6
NPTXFSAV[15:0]
r r r
RM0430 Rev 8
21 20 19 18
NPTQXSAV[7:0]
r r r r
5 4 3 2
r r r r
17 16
r r
1 0
r r
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