ST STM32F423 Reference Manual page 1114

Controller area network (bxCAN)
Bit 8 EWGIE
Bit 7 Reserved, must be kept at reset value.
Bit 6 FOVIE1
Bit 5 FFIE1
Bit 4 FMPIE1
Bit 3 FOVIE0
Bit 2 FFIE0
Bit 1 FMPIE0
Bit 0 TMEIE
Note: Refer to
CAN error status register (CAN_ESR)
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
r r r
15 14 13
Res. Res. Res. Res.
1114/1324
:
Error warning interrupt enable
0: ERRI bit will not be set when EWGF is set.
1: ERRI bit will be set when EWGF is set.
:
FIFO overrun interrupt enable
0: No interrupt when FOVR is set.
1: Interrupt generation when FOVR is set.
:
FIFO full interrupt enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
:
FIFO message pending interrupt enable
0: No interrupt generated when state of FMP[1:0] bits are not 00b.
1: Interrupt generated when state of FMP[1:0] bits are not 00b.
:
FIFO overrun interrupt enable
0: No interrupt when FOVR bit is set.
1: Interrupt generated when FOVR bit is set.
:
FIFO full interrupt enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
:
FIFO message pending interrupt enable
0: No interrupt generated when state of FMP[1:0] bits are not 00b.
1: Interrupt generated when state of FMP[1:0] bits are not 00b.
:
Transmit mailbox empty interrupt enable
0: No interrupt when RQCPx bit is set.
1: Interrupt generated when RQCPx bit is set.
Section 32.8: bxCAN
28 27 26 25
REC[7:0]
r r r r
12 11 10 9
Res. Res. Res.
interrupts.
24 23 22
r r r
8 7 6
Res. Res. LEC[2:0]
rw
RM0430 Rev 8
21 20 19 18
TEC[7:0]
r r r r
5 4 3 2
Res. BOFF
rw rw r
RM0430
17 16
r r
1 0
EPVF EWGF
r r