Bxcan General Description; Can 2.0B Active Core; Table 215. Can Implementation; Figure 378. Can Network Topology - ST STM32F423 Reference Manual

Controller area network (bxCAN)
Single CAN peripheral configuration:
•
CAN3: Master bxCAN with dedicated Memory Access Controller unit and 512-byte
SRAM memory
See Table
CAN features
SRAM size
Filter banks
32.3

bxCAN general description

In today CAN applications, the number of nodes in a network is increasing and often several
networks are linked together via gateways. Typically the number of messages in the system
(to be handled by each node) has significantly increased. In addition to the application
messages, Network Management and Diagnostic messages have been introduced.
•
An enhanced filtering mechanism is required to handle each type of message.
Furthermore, application tasks require more CPU time, therefore real-time constraints
caused by message reception have to be reduced.
• A receive FIFO scheme allows the CPU to be dedicated to application tasks for a long
time period without losing messages.
The standard HLP (Higher Layer Protocol) based on standard CAN drivers requires an
efficient interface to the CAN controller.
32.3.1

CAN 2.0B active core

The bxCAN module handles the transmission and the reception of CAN messages fully
autonomously. Standard identifiers (11-bit) and extended identifiers (29-bit) are fully
supported by hardware.
1086/1324
215.

Table 215. CAN implementation

CAN1
512-byte shared between the two bxCAN
26 filter banks shared between CAN1 and CAN2 14 fiter banks

Figure 378. CAN network topology

CAN2
RM0430 Rev 8
RM0430
CAN3
512-byte