33.15.33 Otg Device In Endpoint Common Interrupt Mask Register; (Otg_Diepmsk) - ST STM32F423 Reference Manual

RM0430

33.15.33 OTG device IN endpoint common interrupt mask register

(OTG_DIEPMSK)

Address offset: 0x810
Reset value: 0x0000 0000
This register works with each of the OTG_DIEPINTx registers for all endpoints to generate
an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the
OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register.
Status bits are masked by default.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. NAKM Res.
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 NAKM: NAK interrupt mask
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 Reserved, must be kept at reset value.
Bit 8 TXFURM: FIFO underrun mask
Bit 7 Reserved, must be kept at reset value.
Bit 6 INEPNEM: IN endpoint NAK effective mask
Bit 5 INEPNMM: IN token received with EP mismatch mask
Bit 4 ITTXFEMSK: IN token received when Tx FIFO empty mask
Bit 3 TOM: Timeout condition mask (Non-isochronous endpoints)
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
USB on-the-go full-speed (OTG_FS)
24 23 22
Res. Res. Res.
8 7 6
TXFU INEPN INEPN
Res.
RM EM
rw rw
RM0430 Rev 8
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
ITTXFE
TOM Res.
MM MSK
rw rw rw
17 16
Res. Res.
1 0
XFRC
EPDM
M
rw rw
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