Otg Receive Fifo Size Register (Otg_Grxfsiz); Otg Host Non-Periodic Transmit Fifo Size Register (Otg_Hnptxfsiz)/Endpoint 0 Transmit Fifo Size; (Otg_Dieptxf0) - ST STM32F423 Reference Manual

USB on-the-go full-speed (OTG_FS)
33.15.9

OTG receive FIFO size register (OTG_GRXFSIZ)

Address offset: 0x024
Reset value: 0x0000 0200
The application can program the RAM size that must be allocated to the Rx FIFO.
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 RXFD[15:0]: Rx FIFO depth
33.15.10 OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size

(OTG_DIEPTXF0)

Address offset: 0x028
Reset value: 0x0200 0200
31 30 29
rw rw rw
15 14 13
rw rw rw
Host mode
Bits 31:16 NPTXFD[15:0]: Non-periodic Tx FIFO depth
This value is in terms of 32-bit words.
Minimum value is 16
Programmed values must respect the available FIFO memory allocation and must not
exceed the power-on value.
Bits 15:0 NPTXFSA[15:0]: Non-periodic transmit RAM start address
This field configures the memory start address for non-periodic transmit FIFO RAM.
1180/1324
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
This value is in terms of 32-bit words.
Minimum value is 16
Programmed values must respect the available FIFO memory allocation and must not
exceed the power-on value.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
RXFD[15:0]
rw rw rw
24 23 22
NPTXFD/TX0FD[15:0]
rw rw rw
8 7 6
NPTXFSA/TX0FSA[15:0]
rw rw rw
RM0430 Rev 8
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0430
17 16
Res. Res.
1 0
rw rw
17 16
rw rw
1 0
rw rw