Otg Host Channel X Interrupt Mask Register (Otg_Hcintmskx); (X = 0 - ST STM32F423 Reference Manual

USB on-the-go full-speed (OTG_FS)
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 DTERR: Data toggle error.
Bit 9 FRMOR: Frame overrun.
Bit 8 BBERR: Babble error.
Bit 7 TXERR: Transaction error.
Indicates one of the following errors occurred on the USB.
CRC check failure
Timeout
Bit stuff error
False EOP
Bit 6 Reserved, must be kept at reset value.
Bit 5 ACK: ACK response received/transmitted interrupt.
Bit 4 NAK: NAK response received interrupt.
Bit 3 STALL: STALL response received interrupt.
Bit 2 Reserved, must be kept at reset value.
Bit 1 CHH: Channel halted.
Indicates the transfer completed abnormally either because of any USB transaction error or
in response to disable request by the application.
Bit 0 XFRC: Transfer completed.
Transfer completed normally without any errors.

33.15.27 OTG host channel x interrupt mask register (OTG_HCINTMSKx)

(x = 0..11, where x = Channel number)
Address offset: 0x50C + (x * 0x20)
Reset value: 0x0000 0000
This register reflects the mask for each channel status described in the previous section.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
1198/1324
28 27 26 25
Res. Res. Res.
12 11 10 9
DTERR FRM
Res.
M ORM
rw rw
24 23 22
Res. Res. Res.
8 7 6
BBERR TXERR
Res. ACKM
M M
rw rw
RM0430 Rev 8
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
STALL
NAKM Res.
M
rw rw rw
RM0430
17 16
Res. Res.
1 0
XFRC
CHHM
M
rw rw