33.15.34 Otg Device Out Endpoint Common Interrupt Mask Register; (Otg_Doepmsk) - ST STM32F423 Reference Manual

USB on-the-go full-speed (OTG_FS)
Bit 2 Reserved, must be kept at reset value.
Bit 1 EPDM: Endpoint disabled interrupt mask
Bit 0 XFRCM: Transfer completed interrupt mask

33.15.34 OTG device OUT endpoint common interrupt mask register

(OTG_DOEPMSK)

Address offset: 0x814
Reset value: 0x0000 0000
This register works with each of the OTG_DOEPINTx registers for all endpoints to generate
an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the
OTG_DOEPINTx register can be masked by writing into the corresponding bit in this
register. Status bits are masked by default.
31 30 29
Res. Res. Res. Res.
15 14 13
NYET NAK BERR
Res.
MSK MSK
rw rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 NYETMSK: NYET interrupt mask
Bit 13 NAKMSK: NAK interrupt mask
Bit 12 BERRM: Babble error interrupt mask
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 Reserved, must be kept at reset value.
Bit 8 OUTPKTERRM: Out packet error mask
Bit 7 Reserved, must be kept at reset value.
Bit 6 Reserved, must be kept at reset value.
1206/1324
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
M
rw
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
24 23 22
Res. Res. Res.
8 7 6
OUT
PKT Res. Res. PHSR
ERRM
rw
RM0430 Rev 8
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
STS
OTEPD STUPM Res.
XM M
rw rw rw
RM0430
17 16
Res. Res.
1 0
XFRC
EPDM
M
rw rw