Otg Host Port Control And Status Register (Otg_Hprt) - ST STM32F423 Reference Manual

USB on-the-go full-speed (OTG_FS)

33.15.24 OTG host port control and status register (OTG_HPRT)

Address offset: 0x440
Reset value: 0x0000 0000
This register is available only in host mode. Currently, the OTG host supports only one port.
A single register holds USB port-related information such as USB reset, enable, suspend,
resume, connect status, and test mode for each port. It is shown in
bits in this register can trigger an interrupt to the application through the host port interrupt
bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a port interrupt, the
application must read this register and clear the bit that caused the interrupt. For the rc_w1
bits, the application must write a 1 to the bit to clear the interrupt.
31 30 29
Res. Res. Res. Res.
15 14 13
PTCTL[2:0] PPWR
rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:17 PSPD[1:0]: Port speed
Indicates the speed of the device attached to this port.
01: Full speed
10: Low speed
11: Reserved
Bits 16:13 PTCTL[3:0]: Port test control
The application writes a nonzero value to this field to put the port into a Test mode, and the
corresponding pattern is signaled on the port.
0000: Test mode disabled
0001: Test_J mode
0010: Test_K mode
0011: Test_SE0_NAK mode
0100: Test_Packet mode
0101: Test_Force_Enable
Others: Reserved
Bit 12 PPWR: Port power
The application uses this field to control power to this port, and the core clears this bit on an
overcurrent condition.
0: Power off
1: Power on
Bits 11:10 PLSTS[1:0]: Port line status
Indicates the current logic level USB data lines
Bit 10: Logic level of OTG_DP
Bit 11: Logic level of OTG_DM
Bit 9 Reserved, must be kept at reset value.
1194/1324
28 27 26 25
Res. Res. Res.
12 11 10 9
PLSTS[1:0] Res.
rw r r
24 23 22
Res. Res. Res.
8 7 6
PRST PSUSP PRES
CHNG
rw rs rw rc_w1
RM0430 Rev 8
Figure 403. The rc_w1
21 20 19 18
Res. Res. Res. PSPD[1:0]
r
5 4 3 2
POC PEN
POCA PENA
CHNG
r rc_w1 rc_w1
RM0430
17 16
PTCTL
[3]
r rw
1 0
PCDET PCSTS
rc_w1 r