Sai Xframe Configuration Register (Sai_Xfrcr) Where X Is A Or B - ST STM32F423 Reference Manual

Serial audio interface (SAI)
30.17.3

SAI xFrame configuration register (SAI_XFRCR) where x is A or B

Address offset: Block A: 0x00C
Address offset: Block B: 0x02C
Reset value: 0x0000 0007
Note: This register has no meaning in AC'97 audio protocol
31 30 29 28
15 14 13 12
Res.
rw rw rw
Bits 31:19 Reserved, always read as 0.
Bit 18 FSOFF: Frame synchronization offset. This bit is set and cleared by software.
0: FS is asserted on the first bit of the slot 0.
1: FS is asserted one bit before the first bit of the slot 0.
This bit has no meaning and is not used in AC'97 audio block configuration.
This bit must be configured when the audio block is disabled.
Bit 17 FSPOL: Frame synchronization polarity. This bit is set and cleared by software
0: FS is active low (falling edge)
1: FS is active high (rising edge)
This bit is used to configure the level of the start of frame on the FS signal.
This bit has no meaning and is not used in AC'97 audio block configuration.
This bit must be configured when the audio block is disabled.
Bit 16 FSDEF: Frame synchronization definition. This bit is set and cleared by software.
0: FS signal is a start frame signal
1: FS signal is a start of frame signal + channel side identification
When the bit is set, the number of slots defined in the SAI_ASLOTR register has to be even. It
means that there will be half of this number of slots dedicated for the left channel and the other slots
for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...)
This bit has no meaning and is not used in AC'97 audio block configuration.
This bit must be configured when the audio block is disabled.
1016/1324
27 26 25 24
Reserved
11 10 9 8
FSALL[6:0]
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23 22 21
7 6 5
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RM0430 Rev 8
20 19 18 17
FSOFF FSPOL FSDEF
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4 3 2 1
FRL[7:0]
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RM0430
16
r
0
rw