33.15.20 Otg Host Frame Number/Frame Time Remaining Register; (Otg_Hfnum); 33.15.21 Otg_Host Periodic Transmit Fifo/Queue Status Register; (Otg_Hptxsts) - ST STM32F423 Reference Manual

Advanced arm-based 32-bit mcus
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RM0430

33.15.20 OTG host frame number/frame time remaining register

(OTG_HFNUM)

Address offset: 0x408
Reset value: 0x0000 3FFF
This register indicates the current frame number. It also indicates the time remaining (in
terms of the number of PHY clocks) in the current frame.
31
30
29
r
r
r
15
14
13
r
r
r
Bits 31:16 FTREM[15:0]: Frame time remaining
Bits 15:0 FRNUM[15:0]: Frame number

33.15.21 OTG_Host periodic transmit FIFO/queue status register

(OTG_HPTXSTS)

Address offset: 0x410
Reset value: 0x0008 0100
This read-only register contains the free space information for the periodic Tx FIFO and the
periodic transmit request queue.
31
30
29
PTXQTOP[7:0]
r
r
r
15
14
13
r
r
r
28
27
26
25
r
r
r
r
12
11
10
9
r
r
r
r
Indicates the amount of time remaining in the current frame, in terms of PHY clocks. This
field decrements on each PHY clock. When it reaches zero, this field is reloaded with the
value in the Frame interval register and a new SOF is transmitted on the USB.
This field increments when a new SOF is transmitted on the USB, and is cleared to 0 when
it reaches 0x3FFF.
28
27
26
25
r
r
r
r
12
11
10
9
r
r
r
r
USB on-the-go full-speed (OTG_FS)
24
23
22
FTREM[15:0]
r
r
r
8
7
6
FRNUM[15:0]
r
r
r
24
23
22
r
r
r
8
7
6
PTXFSAVL[15:0]
r
r
r
RM0430 Rev 8
21
20
19
18
r
r
r
r
5
4
3
2
r
r
r
r
21
20
19
18
PTXQSAV[7:0]
r
r
r
r
5
4
3
2
r
r
r
r
17
16
r
r
1
0
r
r
17
16
r
r
1
0
r
r
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