Otg Device In Endpoint X Control Register (Otg_Diepctlx); (X = 1 - ST STM32F423 Reference Manual

RM0430
Bit 21 STALL: STALL handshake
Bit 20 Reserved, must be kept at reset value.
Bits 19:18 EPTYP: Endpoint type
Bit 17 NAKSTS: NAK status
Bit 16 Reserved, must be kept at reset value.
Bit 15 USBAEP: USB active endpoint
Bits 14:2 Reserved, must be kept at reset value.
Bits 1:0 MPSIZ[1:0]: Maximum packet size

33.15.41 OTG device IN endpoint x control register (OTG_DIEPCTLx)

(x = 1..5 , where x = endpoint number)
Address offset: 0x900 + (x * 0x20)
Reset value: 0x0000 0000
The application uses this register to control the behavior of each logical endpoint other than
endpoint 0.
31 30 29
SD0
SODD PID/
EPENA EPDIS
FRM SEVN
FRM
rs rs w
15 14 13
USBA
Res. Res. Res.
EP
rw
The application can only set this bit, and the core clears it when a SETUP token is received
for this endpoint. If a NAK bit, a Global IN NAK or Global OUT NAK is set along with this bit,
the STALL bit takes priority.
Hardcoded to '00' for control.
Indicates the following:
0: The core is transmitting non-NAK handshakes based on the FIFO status
1: The core is transmitting NAK handshakes on this endpoint.
When this bit is set, either by the application or core, the core stops transmitting data, even
if there are data available in the Tx FIFO. Irrespective of this bit's setting, the core always
responds to SETUP data packets with an ACK handshake.
This bit is always set to 1, indicating that control endpoint 0 is always active in all
configurations and interfaces.
The application must program this field with the maximum packet size for the current logical
endpoint.
00: 64 bytes
01: 32 bytes
10: 16 bytes
11: 8 bytes
28 27 26 25
SNAK CNAK
w w w rw
12 11 10 9
Res.
rw rw
USB on-the-go full-speed (OTG_FS)
24 23 22
TXFNUM[3:0] STALL
rw rw rw
8 7 6
MPSIZ[10:0]
rw rw rw
RM0430 Rev 8
21 20 19 18
Res. EPTYP[1:0]
rw/rs rw rw
5 4 3 2
rw rw rw rw
17 16
EO
NAK
NUM/
STS
DPID
r r
1 0
rw rw
1211/1324
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