Rcc Cpu2 Apb3 Peripheral Clock Enable In Sleep Mode Register (Rcc_C2Apb3Smenr) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Reset and clock control (RCC)

Bit 10 Reserved, must be kept at reset value.

Bit 9 ADCSMEN: ADC clocks enable during CPU2 CSleep and CStop modes

This bit is set and cleared by software.

0: ADC bus clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: ADC bus clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

Bits 8:0 Reserved, must be kept at reset value.

RCC CPU2 APB3 peripheral clock enable in Sleep mode register

(RCC_C2APB3SMENR)

Address offset: 0x184

Reset value: 0x0000 0001

Access: word, half-word and byte access

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 SUBGHZSPISMEN: sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes

This bit is set and cleared by software.

0: Sub-GHz radio SPI clock disabled by the clock gating during CPU2 CSleep and CStop

1: Sub-GHz radio SPI clock enabled by the clock gating during CPU2 CSleep mode,

disabled during CPU2 CStop mode

RM0453 Rev 1

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