ST STM32WL5 Series Reference Manual page 336

Reset and clock control (RCC)
Bit 11 LSESYSRDY: LSE system clock ready
This bit is set and cleared by hardware to indicate when the LSE system clock is ready after
the LSESYSEN bit is set. This bit is only valid when LSEON, LSERDY and LSESYSEN are
set.
0: LSE system clock not ready
1: LSE system clock ready
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
These bits are set by software to select the clock source for the RTC. Once the RTC clock
source is selected, it cannot be changed anymore unless the Backup domain is reset, or
unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset
them.
These bits cannot be written when LSE clock security is enabled in LSECSSON.
00: No clock
01: LSE oscillator clock selected
10: LSI oscillator clock selected
11: HSE32 oscillator clock divided by 32 selected
Bit 7 LSESYSEN: LSE system clock enable
This bit is set and cleared by software to enabled the LSE as system clock to the USARTx,
LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode. The LSE system clock
is only enabled when LSEON and LSERDY are both set.
0: LSE system clock disabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO,
MCO, MSI PLL mode
1: LSE system clock enabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO,
MCO, MSI PLL mode
Note: The LSE clock for the RTC is not impacted by this bit.
Bit 6 LSECSSD: CSS on LSE failure detection
This bit is set by hardware to indicate when a failure is detected by the CSS on the external
32 kHz oscillator (LSE). This bit is only reset by hardware on a BDRST and a POR reset.
0: No failure detected on LSE (32 kHz oscillator)
1: Failure detected on LSE (32 kHz oscillator)
Bit 5 LSECSSON: CSS on LSE enable
This bit is set by software to enable the CSS on LSE (32 kHz oscillator). LSECSSON must
be enabled after the LSE oscillator is enabled (LSEON bit = 1) and ready (LSERDY flag set
by hardware), and after the RTCSEL bit is selected. This bit automatically enables the LSI
oscillator. Once enabled this bit cannot be disabled, except after a LSE failure detection
(LSECSSD = 1). In that case the software must disable the LSECSSON bit.
0: CSS on LSE off
1: CSS on LSE on
Bits 4:3 LSEDRV[1:0]: LSE oscillator drive capability
These bits are set by software to modulate the LSE oscillator drive capability.
00: Xtal mode lower driving capability
01: Xtal mode medium-low driving capability
10: Xtal mode medium-high driving capability
11: Xtal mode higher driving capability
Note: The oscillator is in Xtal mode when it is not in bypass mode.
336/1461 RM0453 Rev 1
RM0453