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ST STM32WL5 Series Reference Manual page 360

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Reset and clock control (RCC)

Off-

Register

set

RCC_

AHB1SMENR

0x068

Reset value

RCC_

AHB2SMENR

0x06C

Reset value

RCC_

AHB3SMENR

0x070

Reset value

0x074

Reserved

RCC_APB1

SMENR1

0x078

1

Reset value

RCC_APB1

SMENR2

0x07C

Reset value

RCC_APB2

SMENR

0x080

Reset value

360/1461

Table 63. RCC register map and reset values (continued)

1 1 1

1

1 1 1

1 1 1

Reserved

1

1

1 1

1

RM0453 Rev 1

1

1

1 1

1 1

1 1

1

RM0453

1 1 1

1 1 1

1

1

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