Rcc Cpu2 Ahb3 Peripheral Clock Enable Register (Rcc_C2Ahb3Enr) - ST STM32WL5 Series Reference Manual

Reset and clock control (RCC)
7.4.35 RCC CPU2 AHB3 peripheral clock enable register
(RCC_C2AHB3ENR)
Address offset: 0x150
Reset value: 0x0208 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access from
CPU2 is not supported.
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 FLASHEN: CPU2 Flash memory interface clock enable
Bits 24:21 Reserved, must be kept at reset value.
Bit 20 IPCCEN: CPU2 IPCC interface clock enable
Bit 19 HSEMEN: CPU2 HSEM clock enable
Bit 18 RNGEN: CPU2 True RNG clocks enable
Bit 17 AESEN: CPU2 AES accelerator clock enable
Bit 16 PKAEN: CPU2 PKA accelerator clock enable
Bits 15:0 Reserved, must be kept at reset value.
344/1461
28 27 26 25
FLASH
Res. Res. Res.
EN
rw
12 11 10 9
Res. Res. Res. Res.
This bit can only be cleared when the Flash memory is in power down. It is set and cleared
by software.
0: Flash memory interface clock disabled for CPU2
1: Flash memory interface clock enabled for CPU2
This bit is set and cleared by software.
0: IPCC clock disabled for CPU2
1: IPCC clock enabled for CPU2
This bit is set and cleared by software.
0: HSEM clock disabled for CPU2
1: HSEM clock enabled for CPU2
This bit is set and cleared by software.
0: True RNG bus and kernel clocks disabled for CPU2
1: True RNG bus and kernel clocks enabled for CPU2
This bit is set and cleared by software.
0: AES clock disabled for CPU2
1: AES clock enabled for CPU2
This bit is set and cleared by software. PKA clock is enabled when a hardware PKA SRAM
erase is ongoing.
0: PKA clock disabled for CPU2
1: PKA clock enabled for CPU2
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0453 Rev 1
21 20 19 18
IPCC HSEM RNG
Res.
EN EN EN
rw rw rw
5 4 3 2
Res. Res. Res. Res.
RM0453
17 16
AES PKA
EN EN
rw rw
1 0
Res. Res.