Ipcc Processor 1 Mask Register (Ipcc_C1Mr) - ST STM32WL5 Series Reference Manual

RM0453
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 TXFIE: Processor 1 transmit channel free interrupt enable
Associated with IPCC_C1TOC2SR.
1: Enable an unmasked processor 1 transmit channel free to generate a TX free interrupt.
0: Processor 1 TX free interrupt disabled
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 RXOIE: Processor 1 receive channel occupied interrupt enable
Associated with IPCC_C2TOC1SR.
1: Enable an unmasked processor 1 receive channel occupied to generate an RX occupied
interrupt.
0: Processor 1 RX occupied interrupt disabled
9.4.2

IPCC processor 1 mask register (IPCC_C1MR)

Address offset: 0x004
Reset value: 0xFFFF FFFF
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:16 CHnFM: Processor 1 transmit channel n status set, (n = 6 to 1).
Associated with IPCC_C1TOC2SR.CHnF
1: Transmit channel n free interrupt masked.
0: Transmit channel n free interrupt not masked.
Bits 15:6 Reserved, must be kept at reset value.
Bits 5:0 CHnOM: Processor 1 receive channel n status clear (n = 6 to 1).
Associated with IPCC_C2TOC1SR.CHnF
1: Receive channel n occupied interrupt masked.
0: Receive channel n occupied interrupt not masked.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Inter-processor communication controller (IPCC)
24 23 22 21
CH6
Res. Res. Res.
FM
rw
8 7 6
CH6
Res. Res. Res.
OM
rw
RM0453 Rev 1
20 19 18
CH5 CH4 CH3
FM FM FM
rw rw rw
5 4 3 2
CH5 CH4 CH3
OM OM OM
rw rw rw
17 16
CH2 CH1
FM FM
rw rw
1 0
CH2 CH1
OM OM
rw rw
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