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Hardware semaphore (HSEM)
8.4.3
HSEM interrupt enable register (HSEM_CnIER)
Address offset: 0x100 + 0x010 * (n - 1), (n = 1 to 2)
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ISE[15:0]: Interrupt(n) semaphore x enable bit (x = 0 to 15)
8.4.4
HSEM interrupt clear register (HSEM_CnICR)
Address offset: 0x104 + 0x010 * (n - 1), (n = 1 to 2)
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ISC[15:0]: Interrupt(n) semaphore x clear bit (x = 0 to 15)
8.4.5
HSEM interrupt status register (HSEM_CnISR)
Address offset: 0x108 + 0x010 * (n - 1), (n = 1 to 2)
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
r
r
r
374/1461
28
27
26
25
Res.
Res.
Res.
12
11
10
9
rw
rw
rw
rw
This bit is read and written by software.
0: Interrupt(n) generation for semaphore x disabled (masked)
1: Interrupt(n) generation for semaphore x enabled (not masked)
28
27
26
25
Res.
Res.
Res.
12
11
10
9
rc_w1
rc_w1
rc_w1
This bit is written by software, and is always read 0.
0: Interrupt(n) semaphore x status ISFx and masked status MISFx not affected.
1: Interrupt(n) semaphore x status ISFx and masked status MISFx cleared.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
r
r
r
r
24
23
22
Res.
Res.
Res.
8
7
6
ISE[15:0]
rw
rw
rw
24
23
22
Res.
Res.
Res.
8
7
6
ISC[15:0]
rc_w1
rc_w1
rc_w1
rc_w1
24
23
22
Res.
Res.
Res.
8
7
6
ISF[15:0]
r
r
r
RM0453 Rev 1
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
rw
rw
rw
rw
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
rc_w1
rc_w1
rc_w1
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
r
r
r
r
RM0453
17
16
Res.
Res.
1
0
rw
rw
17
16
Res.
Res.
1
0
rc_w1
rc_w1
17
16
Res.
Res.
1
0
r
r
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