ST STM32WL5 Series Reference Manual page 297

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Table of Contents

1. x = Don't care.

2. Depends on EXTI CPU2 CDBGPWRUPREQ wakeup event setting.

3. Depends on EXTI CPU1 CDBGPWRUPREQ wakeup event setting.

When leaving the Stop modes (Stop 0, Stop 1 or Stop 2), the system clock is either MSI or

HSI16, depending on the software configuration of the STOPWUCK bit in the

configuration register

Stop mode, the C2HPRE[3:0] bits in the

(RCC_EXTCFGR)

SYSCLK clock without any division. The frequency (range and user trim) of the MSI

oscillator is the one configured before entering Stop mode. The user trim of HSI16 is kept. If

the MSI was in PLL-mode before entering Stop mode, the PLL-mode stabilization time must

be waited for after wakeup, even if LSE was kept on during the Stop mode.

When exiting Standby mode, the system clock is MSI at 4 MHz.

When exiting Shutdown modes, the system clock is MSI. The MSI frequency at wakeup

from Shutdown mode is 4 MHz. The user trim is lost.

If a Flash memory programming operation is ongoing, Stop, Standby and Shutdown modes

entry is delayed until the Flash memory interface access is finished. If an access to the APB

domain is ongoing, Stop, Standby and Shutdown modes entry is delayed until the APB

access is finished.

Table 62. Low-power debug configurations

(RCC_CFGR). If STOPWUCK selects the HSI16 clock when exiting

are reset. This results in the HCLK2 clock directly driven from the

RM0453 Rev 1

RCC extended clock recovery register

Reset and clock control (RCC)

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