Low-Power Modes; Table 62. Low-Power Debug Configurations - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Reset and clock control (RCC)
7.3

Low-power modes

AHB and APB peripheral clocks, including DMA clock, can be disabled by software.
Sleep and LPSleep modes stop the CPU clock. The memory interface clocks (Flash
memory and SRAM1/2 interfaces) can be stopped during Sleep mode by software using the
SRAMxSMEN bits. The AHB to APB bridge clocks are disabled by hardware during Sleep
mode when all the clocks of the peripherals connected to them are disabled in the
peripheral SMEN bits.
Stop modes (Stop 0, Stop 1 and Stop 2) stop most clocks in the V
the PLLs, the MSI and the HSE32 oscillators. HSI16 may be kept running when requested
by the peripheral (USART1, USART2, LPUART1, I2C1, I2C2 or I2C3) that allows the
wakeup from Stop modes.
All U(S)ARTs, LPUARTs and I2Cs have the capability to enable the HSI16 oscillator even
when the MCU is in Stop mode (if HSI16 is selected as clock source for that peripheral).
All U(S)ARTs, LPUARTs and LPTIMs can also be driven by the LSE oscillator when the
system is in Stop mode (if LSE is selected as clock source for that peripheral) and the LSE
oscillator is enabled (LSEON). In that case, LSE remains always on in Stop mode (no
capability to turn on the LSE oscillator).
All LPTIMs can also be driven by the LSI oscillator when the system is in Stop mode (if LSI
is selected as clock source for that peripheral) and the LSI oscillator is enabled (LSION).
Standby and Shutdown modes stop all clocks in the V
HSI16, the MSI and the HSE32 oscillators.
The low-power modes can be overridden for debugging the CPU1 by setting the
DBG_SLEEP, DBG_STOP or DBG_STANDBY bits in the DBGMCU_CR register. In
addition, the EXTI CDBGPWRUPREQ events can be used to allow debugging the CPUs in
Stop modes (see the table below).
Mode
Sleep
Stop 0
and
Stop 1
Stop 0,
Stop 1
and
Stop 2
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Table 62. Low-power debug configurations

CDBGPW
RUPREQ
CPU1
CPU2
STANDBY
(1)
x
x
Disabled
x
Enabled
Disable
d
x
Enabled
Disable
d
x
Enabled
CORE
DBGMCU
DBG_
DBG_STOP
x
x
Disabled
x
Enabled
RM0453 Rev 1
domain and disable
CORE
domain and disable the PLL, the
Debug
DBG_
CPU1
SLEEP
x
Enabled
Disabled
Enabled
(3)
-
x
Enabled
RM0453
CPU2
Enabled
(2)
-
Disabled
Enabled
Disabled
Enabled

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